Semiconductor fabrication, tungsten silicide (WSi.sub.x) has developed as a leading conductive layer to be formed on a polysilicon layer for improved conductivity. Various etching chemistries have been developed to pattern the Wsi.sub.x /polysilicon stack to form such conductors as the digitline or wordline used in memory devices.
Memory devices have become very densely packed as the storage capability of each device has increased. In that light, it becomes important to etch substantially vertical lines within minimum feature widths. The majority of etching in tight spaces is accomplished by accelerating ions across a cathode sheath which are highly directional and thus make it to the bottom of tight spaces much easier than neutrals that move in all directions. However, the typical etching chemistry, like SF.sub.6, CF.sub.4, CHF.sub.3 or C.sub.2 F.sub.6, will lose etching momentum in tight areas relative to open areas due to the deposition of sulfur or carbon in the tight areas relative to open areas. This phenomenon is known as micro-loading and is undesirable.
There are several possibilities which may cause micro-loading. One possible cause of micro-loading may be deposition due to the lack of sufficient neutrals in the tight areas to recombine with the deposited material to form volatile species that can be removed from the chamber. Another possibility may be due to ions reflecting off of the photoresist side walls that may cause more deposition matter buildup in tight areas than in open areas. Regardless of the cause for micro-loading, an etching chemistry for etching WSi.sub.x is needed that will minimize, if not eliminate micro-loading effects. The present invention addresses this very issue by teaching a new WSi.sub.x etching chemistry that does minimizes micro-loading.